The role involves covering primary DFT activities of 

  • Architecture
  • RTL
  • MBIST/BISR insertion and simulation
  • Scan insertion
  • AMS simulation
  • STA test constraints
  • debug and vector generation
  • ATE test program development

The following are required:

  • Degree in Electrical Engineering, Computer Engineering or other relevant technical area
  • at least 5 years of full time DFT experience
  • Verilog and VHDL RTL coding
  • TCL scripting
  • At least one scripting language such as Perl or Python
  • Knowledge of IEEE1149.1, IEEE1500, IEEE1687
  • Boundary Scan insertion
  • DFT verification experience
  • Scan insertion (including scan isolation wrapper, OCC and IO-sharing), preferably using Synopsys flow
  • ATPG generation (preferably with Synopsys TetraMAX) and validation
  • Direct experience on Silicon debugging/bring-up of DFT tests
  • MBIST insertion and validation (Mentor flow preferred),
  • Extensive knowledge of the DFT concepts
  • PHY DFT verification
  • Very good collaboration and communication skills

The following skills are desirable but not essential

  • ATE experience
  • MBIST insertion with Synopsys SMS
  • Ser-Des verification
  • Design Synthesis
  • Verification experience
  • Physical Design experience

Experience: 7+ Years

Location: UK


  • Highly competitive to match experience and capability

How To Apply: Send your CV to [email protected]