- Good understanding of complete VLSI design cycle
- Strong 2+ years of Testbench and Test development experience using System Verilog/UVM
- Must be familiar with verification methodologies like OVM/UVM
- Good knowledge in C/C++/ system Verilog and scripting (Perl & TCL)
- Good knowledge of AMBA, AHB/AXI protocol, High Speed Protocols – PCI, Ethernet.
- Good debugging skills
- Video Codecs knowledge is an added advantage
- Excellent communication skills.
- B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major
- 2+ Years
- Highly competitive to match experience and capability