Job Code: HWDUSA060717_22
- You will be a part of customer Connectivity organization responsible for development of SoC designs.
- You will be also involved in the timing constraint development, synthesis, DFT of subsystems, logic equivalency checks, and static low power checks for isolation and level shifter implementations.
- You will be responsible for RTL integration of various SoC designs, perform various Lint checks to make sure coding guidelines are met for proper synthesizable RTL, compatible for DFT and Low Power.
- You will be also involved in the timing constraint development, synthesis and DFT of subsystems, logic equivalency checks, static low power checks for isolation and level shifter implementations.
- You will be responsible for reviews related to timing constraints, synthesis results, DFT coverage results with the team.
- You will provide feedback to designers of any DFT, synthesis, low power, and timing issues that need to be addressed.
- You will be also involved in the static timing analysis of subsystems and full chip on preroute and postroute databases.
- You will be responsible for power analysis using tools like Power Artist and PTPX for subsystems and entire chip by working with the lead engineer.
- 7 years of experience with Verilog ASIC design and ASIC implementation related to postRTL
- Experience with Synopsys tools for ASIC synthesis, DFT and static timing analysis is a must.
- Experience with Logic equivalency checks is a must.
- Experience with static low power checks is preferred.
- Experience with fullchip static timing analysis through tapeout is a plus.
- Must have worked on at at least one SoC design with direct participation in Timing constraints, Synthesis, and DFT.
- Experience with Power Artist and/or PTPX tools for power analysis is preferred.
- Experience with memory BIST insertion and simulations is a plus.
- Innovative, selfdirected and selfmotivated team player able to thrive in a fastpaced,
organic engineering environment.
- Good verbal and written communication skills.
- Exposure to System Verilog, Perl/Tcl/Makefile scripting
Education: Required: Bachelor’s, Computer Engineering and/or Electrical Engineering Preferred: Master’s, Computer Engineering and/or Electrical Engineering or equivalent experience.
Job Status: Full Time
Work Location: California – Bay Area
- Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]