Job Title:

Test and Verification Engineer

Job Code:


Required skills and experience:

  • Minimum 3 years industry experience.
  • Experience using Standard EDA Tools like Logic Vision, Mentor and Synopsys.
  • Experience in usage of EDA tools for ATPG tools (Tetramax/Fastscan/ET) or Memory BIST, simulation tools (NCSIM/VCS), DFT insertion (eg, Design or RTL Compilers)
  • Strong understanding & hands on experience with industry standard DFT techniques such as boundary scan, Memory BIST, BISA and BIRA, Scan/ Compression/ ATPG/ At-speed Fault simulation and Logic BIST and BIST for high speed serial links.
  • Post Silicon Validation, ATE Debug and Support are needed.

Desired skills and experience:

  • Ideal Candidate will be part of the DFT team, providing DFT services to a wide range of silicon companies. He/She will work on all aspects of DFT (Logic BIST, Memory BIST, Boundary Scan, High speed interface BIST, Full Scan, Scan compression, ATPG and ATE Support).


  • You will be responsible for delivering against that test strategy and providing feedback on the strategy
  • Work as a part of the chip DFT team on DFT RTL create, DFT verification and test pattern delivery activities through the complete design cycle and post-silicon
  • Meet or Exceed test goals
  • Work with cross-domain counterparts to identify and meet any cross-domain inputs/deliverables.
  • Create reusable process/flow infrastructure and good documentation.

This is an excellent opportunity to join a world-class verification company. The remuneration package will reflect this.


  • Bristol based but required to travel/work at client premises in the UK


  • £40,000 to £55,000


  • 45 hours per week
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