Careers

Job Description

• Work as part of a team and implement parts of test bench using System Verilog UVM.
• Develop System Verilog models for complex arithmetic or logic operations, scoreboards, monitors.
• Efficiently debug SV model or c-model or RTL.
• Analyzing test regression fails, debugging and fixing existing code as well.

Past Experience

• Senior Digital Verification Engineer (minimum 4 years of experience in Verification).
• Must be available for at least 1 year, preferably longer.
• Must be able to stick to deadlines and manage time accordingly to ensure quality is maintained.
• Must be adaptable and a quick learner and a very good team player – able to work with engineers from different experience level.
• A self-starter (works well in a team but good at owning tasks).
• Excellent communication skills.
• Familiarity with version management tools.

Location

• Bristol, UK

Experience

• 4+ years

Package

• Highly competitive to match experience and capability