Skill set:

Must Have:

  • Block and Top level verification know-how
  • Verification Plan Development
  • Specman, System Verilog
  • Testbench Development
  • VHDL/Verilog simulation and debug
  • Scripting

Nice to have:

  • HVL: Systemverilog/Specman is a plus
  • End to End RTL Functional Verification Concepts
  • Understanding of power aware architecture

Experience:

  • 4+ Years Of Experience
  • Performing feature extraction from a specification
  • Coverage closure
  • Experience of other HVLs (e.g. System Verilog) and methodologies (e.g. UVM)

Location: UK

Positions: 4

Package

  • Highly competitive to match experience and capability

How To Apply Send your CV to [email protected]