APPLICATION (FRONT – END VERIFICATION) ENGINEER
- He would be supporting world-wide customers with technical guidance like ST, NXP, Intel, Xilinx, Texas, Broadcom and many more.
- Candidate will be working on latest version of simulation tools like irun 15.2 & Xcelium
- Will mainly debug the customer’s issues they are facing with using current tools.
- Candidate should have some knowledge on some VIP protocols also.
- He should have good knowledge of Verilog and System Verilog to resolve customer issues.
- He should have basic knowledge of perls/shell/awk/python scripting.
- Candidate has to resolve customer’s issues through Email support OR Web-ex sessions
- Experience in UVM based verification at IP, Subsystem and SOC level is a plus
- Fundamental SoC Architecture knowledge
- Knowledge of UNIX, scripting language like TCL, perl is a plus
- Strong verbal and written communication skills in English
- Good in debugging skills.
- Self-motivated and strong teamwork skills
- 2 – 5 years
- B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major
- Highly competitive to match experience and capability