Careers

Job Description

• RTL (Verilog/VHDL/SV) for ASIC – IP development or SOC integration.
• Synthesis using DC or genus
• Verilog based Testbench and testcase developments. (ncsim or modelsim)

Qualification

• Any candidate has 3- 6 years on ASIC domain. (NO FPGA)

Skills

• Some VLSI course
• DFT (SCAN, ATPG, BSCAN, MBIST)
• Layout, Memory compiler design or automation
• Knowledge in Clue logic or IP’s for Automotive.
• STA using primetime
• Formal Verification with spyglass or conformal

Experience

• 2+ Years

Location

• Noida

Package

• Highly competitive to match experience and capability