IP Verification Engineer
- Good understanding of completedesign cycle
- Strong 2+ years of Testbench and Test development experience using System Verilog/UVM
- Involved in Front-End IP Verification related to Memory BIST and Memory IPs.
- Must be familiar with verification methodologies like OVM/UVM
- Good to have skills: -SVA, assertion-based verification
- Good knowledge in C/C++/ system Verilog and scripting (Perl & TCL)
- Good knowledge of AMBA, AHB/AXI protocol, High Speed Protocols – PCI, Ethernet.
- Good debugging skills
- Excellent communication skills.
- B.Tech/BE/M.Tech/ME/MSc (Electronics)
- 3+ years
- Highly competitive to match experience and capability