Junior SoC DFT Engineer 2017-04-28T09:37:18+00:00

The role involves covering primary DFT activities of 

  • Architecture
  • RTL
  • MBIST/BISR insertion and simulation
  • Scan insertion
  • AMS simulation
  • STA test constraints
  • debug and vector generation
  • ATE test program development

The following are required:

  • Degree in Electrical Engineering, Computer Engineering or other relevant technical area
  • at least 1 year of full time DFT experience
  • some exposure to Verilog and/or VHDL RTL coding
  • TCL scripting
  • Some exposure to DFT concepts
  • At least one scripting language such as Perl or Python
  • Knowledge of IEEE1149.1, IEEE1500, IEEE1687
  • Some exposure to DFT verification
  • Very good collaboration and communication skills

The following are desirable but not essential

  • Scan insertion, preferably on the Synopsys flow
  • ATPG generation (preferably with Synopsys TetraMAX) and validation
  • Direct experience on Silicon debugging/bring-up of DFT tests
  • MBIST insertion and validation
  • PHY DFT verification
  • ATE experience
  • Boundary Scan insertion
  • Design Synthesis
  • Verification experience
  • Physical Design exposure

Experience: 3+ Years

Location: UK


  • Highly competitive to match experience and capability

How To Apply: Send your CV to [email protected]

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