Post Silicon SOC IP Validation Engineer – JobCode: HWDIND210618_652018-06-21T10:54:04+00:00

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Job Title:

Post Silicon SOC IP Validation Engineer

Job Code:

HWDIND210618_65

Job Description

  • This position will be working directly under the supervision of Hardware Validation and Debug Lead engineer.
  • This engineer will be responsible for creating platform validation test plan for all relevant X86 IPs
  • Platform and CPU / APU bring-up and validation of IP test plan that qualify the features.
  • HW Validation for RAS, DDR with ECC, Ethernet IPs (Gigabit & XGbE) on the SOC (System on Chip) and CPUs
  • HW validation the interfaces and storage technologies like I2S, I2C, USB, PCIe UART, SATA, SSD, NVMe.                                                                                                                                                                                                                                                                                                                  

Qualifications

  • Engineering degree in Electrical/Electronics/Computer science with 4-8 years of relevant experience and strong technical skills.
  • Hands-on debugging experience with JTAG / Trace32 is required on test equipment like Logic analyzer, Oscilloscope and Protocol analyzers.
  • Experience in SOC / Platform Bring-up and debugging bring-up failures.
  • Experience in System level Performance & Power Optimization and measurements.
  • Experience in writing scripts in ruby or PERL.
  • Hands-on experience related to validating one or more of the following is required.
  • X86 Processors & Debug
  • High speed Memories like LPDDR3, DDR4, LPDDR4
  • High speed peripherals like USB 2.0/3.0, eMMC, M.2, SATA, NVMe, PCIe gen-3, and Gigabit Ethernet.
  • Low Speed peripherals like SPI, UART, I2C
  • Multimedia
  • Audio: Soundwire, I2S, PCM.
  • Graphics: GPU, Video Codecs.
  • Display: DP, HDMI, DVI

Experience

  • 4- 8 years

Location

  • Bangalore

Package

  • Highly competitive to match experience and capability
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