RTL Verification Engineer
You will, as part of a project team, take ownership of the verification of particular blocks within the product architecture, moving through all phases of the design and verification flow:
- Creating and reviewing design verification documentation/test plans.
- Designing and implementing verification IP and testbenches.
- Testing and debugging Verilog and System Verilog RTL.
- Planning and tracking tasks to meet the targets at the planned time.
- Working alongside the design team to ensure the quality of the design work done along with on time delivery.
- Substantial experience of RTL verification for complex ASIC products.
- Proficiency in System Verilog / UVM.
- Experience of development of coverage-driven constrained random test environments.
- Willingness to tackle varied and complex technical challenges.
- Excellent communication and written skills in English.
- High level programming experience such as C/C++ and scripting languages, e.g. Perl/TCL/Python.
- Experience of low power RTL design
- Highly competitive to match experience and capability