Helping a leading smartphone manufacturer verify MIPI MPHY Analog IP
About the Customer
The customer is a leader in the smartphone market. Other segments include home appliances, home entertainment and consumer electronics.
The scope of the activity was to model a MIPI MPHY analog IP using Verilog-AMS with wreal and to verify the model using a UVM-MS based testbench environment. The verification of the MPHY model is performed as follows.
Verification is performed first for the standalone analog MPHY model.
Verification is the performed for the analog MPHY model with the client digital MPHY IP to verify the integration and the functions of the combined analog and digital block.
The T&VS Technical Solution
For model development, the client provided T&VS with the design specification, schematics and implementation details for each sub-block of the analog MPHY IP design.
For verification, T&VS took scenario descriptions, test input vectors and output waveforms from a number of client spice simulations. T&VS ported these to the UVM test bench and then compared the UVM results with the reference results. Additionally, T&VS extracted features from the specifications and converted these to directed and constrained random test cases.
The Delivery Model
T&VS executed the project using a phased delivery plan with a “blended” team split between onsite and offshore. The T&VS technical lead shared his time between onsite with the client and offshore leading the T&VS engineers. An offshore project manager performed the planning, reporting, risk management and resource allocation. The client therefore had single technical and management points of contact. The blend of onsite and offshore resources also ensured a cost-effective solution.
The project was executed in three phases with deliverables reviewed at the end of each phase. In the first phase, the spice simulations were analysed and a feature extraction performed to generate a functional coverage proposal. The offshore team also started the analog MPHY IP modelling using Verilog-AMS and building the verification environment using UVM-MS. The phase-1 was signed-off by reviewing the feature extraction, functional coverage document, testbench architecture document, implementation of 50% Verilog-AMS model and bring-up test cases on the model. For Phase-2 signoff, T&VS completed the fully functional Verilog-AMS model and verification completed with 70% functional coverage. For Phase-3, T&VS achieved 100% functional and code coverage closure.
Within three months, T&VS was able to complete the model and achieve 100% functional coverage. T&VS provided regular detailed functional coverage reports and results from checks between the Spice and behavioural model simulations. As part of the T&VS verification process, a detailed VIP user guide and test plan document was shared with the customer.
The Client Benefits
- 100% functional coverage closure within three months
- Blended T&VS model allowed the client to meet strict budget guidelines
- Delivery model tailored to meet customer sign-off requirements