Case Studies

UVM based Verification of a Sensor System-in-Package SOC


The client is one of the world’s leading suppliers of a wide range of analog,  MEMS and sensor semiconductors.

The scope of the project was to undertake the hardware verification of a SOC comprising rotation and acceleration sensors with a bi-directional SPI interface to the MCU.

The T&VS Solution

T&VS undertook the project using the Universal Verification Methodology (UVM) using the Cadence Incisive and vManager Tools.

The verification process included:

  • Developed SV real models for analog blocks and MEMS based sensors
  • Integrating the models with the digital part to create a setup that replicates the actual system more closely
  • Performed system-level simulations
  • Simulations done in UVM based environment with constrained randomization
  • Implemented the MEMS model and testbench for closed-loop simulation
  • Verification of the system with the PLL locked

Benefits of T&VS Solutions

  • An independently verified SOC that meets the requirements of the customer’s tier 1 consumer electronics OEM.
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