Due to the growth in complexity of FPGAs and integration of complex IP, the number of asynchronous clocks within FPGA designs has dramatically increased. It has become increasingly difficult to verify these designs for metastability issues due to asynchronous clock domain crossings (CDC).

Clock domain crossings are a key cause of non-deterministic & random field failures in FPGA based systems, leading to unnecessary cycles of design and debug costing designers both valuable time and resources. This article from Semiwiki describes how to address CDC issues early at RTL for FPGA designs, saving valuable time and costly design re-spins.

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