Divyeshkumar Dhanjibhai Vora of ARM will discuss “Challenges with Power Aware Simulation and Verification Methodologies” at DVClub Europe Conference on 22 September 2015.
He discusses about proposed enhancements like integrated PA models, liberty based assertions and UPF macro support using successive refinement, to fill the quality holes in the PA simulation flow.
As the modelling complexity is increasing, it requires a thorough check to qualify the above said features in the library models.
Divyeshkumar also discusses a library based validation flow which has been developed in-house at ARM to ensure the qualification of the PA behavior of each library cell against the reference vectors.
- Power-aware (PA) simulation overview
- Proposed enhancements in PA simulation
- Library based validation flow
If you want to find out more about Power Aware Simulation and Verification Methodologies, then join us on the 22nd Sept.
You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here