From the early days of the Accellera Portable Standards Working Group (PSWG), it was apparent that trying to satisfy a wide range of users with a single input format would be difficult. Hardware designers and block-level verification teams are used toconcepts such as constraints and biasing whilst most validation engineers using hardware platforms mainly write code for embedded processors in C. Chip-level verification engineers typically sat in the middle, with UVM testbenches and embedded processor code in C. C++ was not commonly used except in conjunction with the SystemC class library to create ESL models.

The PSWG members decided to have a PSS-DSL format and a semantically equivalent PSS-C++ format providing identical functionality. The PSL-C++ option provides no additional functionality; it is supported by a class library that matches the declarative nature of PSS-DSL. It is critical to the PSWG goals that both formats can be mapped by PSS tools to the same internal models.

This whitepaper from Mentor Graphics compares the two formats, recommending PSS-DSL because of its universal vendor support, ease-of-learning, SystemVerilog-like syntax, and conciseness — and because it was defined specifically for specifying PSS models.

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