Title: Extending UVM Methodology for Verifying Mixed-Signal Components

Abstract: As the need to include more embedded analog IP increases in the next generation SOCs, it is a challenge to architect verification environments that can effectively accommodate both digital and analog components.  Leveraging the recent advancements and features provided by the UVM methodology and the new enhancements in simulators, the paper demonstrates how these powerful capabilities provided by the SystemVerilog base classes can be extended to the analog world. Through this paper we explore the infrastructure created to provide analog designers and verification engineers with a methodology that allows them to:

  • Introduce analog verification planning
  • Introduce constraint-random verification for driving analog nodes
  • Model analog stimulus as shaped transaction-based bus functional models
  • Integrate reference models with various abstraction level
  • Sample analog nodes to monitor incoming traffic
  • Introduce assertions on analog nodes
  • Introduce analog code coverage and functional coverage
  • Introduce regression management

In conjunction to elaborating on above features, this paper describes a scalable and reusable methodology for verifying analog IPs.

Biography:  I have been working in the semiconductor industry since 2006, mostly as a verification engineer. I have honed my verification skills, while working on SoC and block level verification of Register Transfer Level (RTL) and synthesized gate net-list. The verification experience was enriched by gaining esoteric knowledge of System Verilog (SV) based methodologies like Verification Methodology Manual (VMM) and Universal Methodology manual (UVM) while working on the development of Verification Intellectual Properties (VIPs) of HDMI (High Definition Media Interface) and PCIe (Peripheral Component Interconnect Express) protocols.

Currently at Synopsys I work as a Senior Corporate Application Engineer responsible for development and deployment of Verification IPs. I am also a member of Verification IP engineering team at Synopsys helping with product planning and development of the HDMI Verification IP.  As part of my job, I conduct customer trainings to educate them with my expertise of verification methodologies such as UVM and VMM. I am regular contributor of technical papers and a speaker in multiple conferences which include Design Verification Conference (DVCON) and Design Automation Conference (DAC).  I leverage my expertise in various areas of functional verification to help create and deploy effective and advanced verification solutions such as UVM based methodology for verifying mixed signal component etc. I have always been intrigued by the challenges of verification, as it involves thinking a step ahead of the design.

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