Title: Digital to Mixed-Signal Verification of Power Management SOCs Using Questa-ADMS
Abstract: AMS and RF designs done in STEricsson have big analog functionalities and a lot of interaction between analog and digital functionalities. The partitioning of these designs makes them particularly difficult to verify. The most accurate solution would be to simulate the complete design with a spice simulator, however, increasing time to market constraints and circuit complexity make this approach impossible.
As STEricsson is a platform company, models have to be compatible with pure digital tools to simulate all the SOCs platform together.
As a consequence, we decided to use a digital centric methodology with real numbers to model the analog functionality.
This presentation will show how we developed the models to verify most of the design connectivity and functionality using the speed of digital simulators. It will then describe how Questa-ADMS was used to cover the electrical behaviour of the design by reusing the digital on top environment. Examples will be taken from a power management SOC.
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