|Designation:||Member of Technical Staff|
|Title:||UVM – Simplify through Reuse|
With ever growing complexity of the chips, it is important to create a scalable and configurable verification environment which enables plug and play. Further, UVM is vast and open framework resulting in inconsistent and non-standard solutions to similar problems.
This presentation discusses some of best practices to use UVM in developing a reusable environment.
Currently working in AMD as the verification lead. 14 years of global experience working with leading firms such as IBM, Wipro, and Agere systems. Experience in RTL Design and Verification of ASICs, FPGAs in the field of Hard Disk Controller(HDC), PCI, ARM based protocols, SDRAM Controller, DDR Memory Controller. Has facilitated and delivered several VLSI Corporate training in the areas of SystemVerilog, UVM, OVM Methodologies.
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