|Designation:||Engineering Manager, Audience Communication|
|Title:||Challenges and Traps in UVM adoption|
This presentation will highlight System Verilog based Constrained Random Verification methodologies and also motivations for moving to UVM from existing Verilog based verification environments and the challenges/benefits of the migration process.
Rambabu Maddali has 12+ years of experience in Verification and Validation currently associated with Audience Communications, leading the team for verification and design. He started off his career at Texas Instruments, where he was responsible for system level scenarios validation using Emulation Platform. Later he joined Infineon Technologies where he worked majorly at top level and sub-system level Verification and Silicon Validation of the mobile platforms and subsequently Lantiq Communications, where he worked on Wire line products, verification using Constrained Random Verification methodology and integrating the SystemC models with Emulation validation.
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