|Speaker:||Ando Ki, R&D Director|
|Presentation Title:||FPGA‐based transaction‐level verification through de facto standard interfaces|
|Abstract||Fast functional verification is a key part of successful SoC , while design to be|
integrated into SoC is getting bigger and complex and this makes verification
process slower and difficult. To deal with this mismatch, FPGA‐based
verification is widely adopted and it includes simulation acceleration and
prototyping. This talk gives FPGA‐based verification methods that use de
facto standard interfaces such as USB3.0/2.0 and PCI‐Express between FPGA
and the host computer. This environment supports cycle‐based simulation,
where HDL simulator runs on the host computer along with DUT (Design
Under Test) in the FPGA. This environment also supports transaction‐based
co‐emulation, where BFM (Bus Functional Model) is used to interface
between DUT and host C program.
|Biography||Speaker is working for Dynalith since early 2000, in which he focused on|
design and verification environment for SoC and embedded system including
FPGA‐based simulation accelerators and large‐scale prototyping systems.
Before joining Dynalith, he took part in development cache coherent
protocol and controllers for multi‐processor systems as a member of senior
researcher in ETRI.