|Designation:||Product Marketing Manager|
|Title:||Verifying A SOC Based on the AMBA Interconnect Using Graph Stimulus|
Abstract: In this presentation, we present an architecture for verifying proper operation and performance of a complex AMBA bus fabric in a dual core ARM® processor system using a combination of SystemVerilog and C software driven test techniques. An advanced graph based solution was deployed that provided the capability for checking full protocol compliance, an engine for continuous traffic generation, precise control and configurability for shaping the form and type of traffic needed to test the fabric. These characteristics are easier to construct, easier to analyze and review, are enable more efficient coverage closure.
Biography: Albert is currently the Product Marketing Manager for the Questa Verification Platform. He has over 20 years of experience designing and verifying ASICs & ARM based SOCs. Currently he is focused on the burgeoning field of Design Verification, where he has published and presented papers at IEEE, ARM Developer’s Conference (now ARM TechCon), DVCon and numerous public seminars worldwide. Previously to Mentor Graphics, he was a senior design engineer at VLSI Technology, design engineer at Intel Corporation and a PMM/TMM/AE at Synopsys. He has a BSEE from California State University and an MBA from Santa Clara University.
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