|Designation:||CEO and Founder|
|Title:||Experiences of ARM Based Soc Verification|
Abstract: Changes in SoC design practices over recent years (e.g. multiple CPUs, clock and power domains, more IP blocks) and the increased amount of software has increased the scope for bugs
Unexpected access conflict between shared resources
Complexities arising out of interaction between subsystems which were verified stand alone
Cache coherency in multi-core system
Interrupt connectivity and Priority scheme
Arbitration priority related issues and access dead-locks
Unexpected HW/SW sequencing
Exception handling conflicts and priority scheme
Multiple power domain region, clock domain crossing
Multiple reset and clock region
In this presentation we classify the bugs into three categories which should be the key focus areas for any SoC verification activity:
Checking the integration between the various building block components
Verifying the sanity of the glue logic
Verifying the system level functionality
This paper outlines some of the key methodologies applied to a generic ARM-based SoC architecture to provide a more effective, efficient SoC verification strategy.
Biography: Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide.
Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.
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