|Designation:||Senior Staff Engineer in Verification|
|Title:||Using Certitude for Relative Functional Qualification of a Re-usable Testbench|
Abstract : The presentation discusses a novel use of Certitude tool to ensure the quality of a reusable testbench does not deteriorate across projects. The flow described in the presentation reuses Certitude results to ensure that adding functionality for reuse doesn’t affect the testbench’s existing functions, in a run that takes about one hour (in contrast to our standard Certitude run taking about 3 weeks), enabling us to run these checks frequently. Since we reuse sign-off Certitude results from a completed project, the flow also makes it possible to run high coverage Certitude regressions early in a project. The frequency & quality of the runs ensure that bugs introduced in the testbench are found quickly, simplifying debug and reducing the risk of finding critical bugs late in the project. The flow was deployed across a significant change to our verification environment and found multiple bugs including 3 serious ones.
Biography: I have been with Infineon for the last 4 years working on TriCore CPU Verification primarily responsible for Random Architectural Test Generation (ISG) for the TriCore CPU. Lately I have also been involved in Functional Qualification of the TriCore CPU Verification Environment and devising methods to reduce the cost of Functional Qualification. Overall, I have a number of years of experience and expertise in verifying complex CPU architectures/micro-architectures, having worked previously on the verification of AMD(x86) &IBM(z-Series Server) processors. I have a BEng in Electronics & Communication Engineering from University of Delhi.
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