|Title:||Measuring the Effectiveness of Verification Environments|
Abstract : Shrinking transistors sizes means more complex design is squeezed into the same area that was used a product generation earlier. The world is aware of Moore’s law for design; but it is more applicable to the verification space today as verification complexity has increased exponentially. There are multitudes of tools (i.e. simulators, methodologies) that tell us how we need to verify our designs and various different metrics that tell us what we have verified.
In a world where “only the paranoid survive”, can we really say that every possible scenario has been covered and verified? NO. We only can understand the risks we are taking and solutions to mitigate those risks. Any tool/framework that helps in identifying these risks early on in the verification cycle, will have a huge impact on the design/product either becoming a revenue generator or being assigned to the dump!
Biography: Yogish Sekhar has over 13 years of Experience of which 10 years in Digital Verification. He has a masters’ degree from University of Edinburgh and has worked in Intel, Wipro in India and Broadcom, ARM here in the UK before taking up his current position at Dialog Semiconductor.
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