Name:Ziyad Hanna
Designation:Senior VP of R&D, Chief Architect and General Manager (Jasper Israel)
Title:Integrating Formal and Simulation Results to See the Full Verification Picture

Abstract : Advanced Formal Technology has grown to address large SOCs and many of the more difficult design and verification challenges. Thus, it’s critical for users to be able to seamlessly integrate results from formal methods with their simulation results to generate comprehensive snapshots and trend analyses of their progress. In this presentation we highlight a use case study on design coverage verification. We will also describe how formal coverage metrics, even for “bounded proofs”, can give users the information they need to accelerate the coverage closure process.

Biography : Ziyad Hanna is responsible for advancing the company’s breakthroughs in formal verification technology, core engines and system architecture. Ziyad has over 20 years of industry experience. Prior to joining Jasper, Ziyad was Intel senior principal engineer and the main leader of the Formal Technology Research and Development Group in the Design and Technology Solutions division at Intel Haifa. While at Intel, Ziyad was instrumental in the development of several generations of formal verification systems used on almost all Intel microprocessor designs since early 1990s. A senior IEEE member, Ziyad has been active in the area of formal verification for over 17 years, and has mentored many research projects with academia and served in various international conferences including SAT, ICCAD, DAC and ICCD. He has published more than 25 articles the formal area and holds 8 patents. He received both his B.Sc. and M.S. degrees in computer science at Tel-Aviv University. He received his Ph.D with research in “Abstract Modelling and Formal Verification of Microprocessors” at the Computing Laboratory of Oxford University.

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