|Designation:||Application Consultant, Verification|
|Title:||Top Tips for Successful Power-Aware Verification|
Abstract : Synopsys has been at the forefront of power-aware verification from the early days. During that time we have been involved in a great many projects and some best practices have emerged. In this short presentation, Bhavesh Patel, Synopsys’ verification specialist for power sensitive designs in the UK, summarises some of these practices in our top tips for more productive UPF verification.
Biography : Bhavesh Patel is the Senior Application Consultant for Synopsys in the UK with special responsibility for Power-aware Verification. After initially working within BT, Bhavesh joined Synopsys at the end of 1999 in order to support users of a variety of project-critical EDA tools, including RTL synthesis and formal equivalence checking. This naturally led to his expertise in hardware and software modelling and eventually to design verification. Bhavesh has been working as the Low Power Verification expert in the UK since Synopys’ acquisition of low-power leaders, Archpro in 2007. Ever since then, Bhavesh has trained and supported users of UPF and power-aware verification flows on numerous significant projects in the UK, Ireland and the Netherlands, and continues to do so. Bhavesh holds an honours degree in Microelectronics from Brunel University in the UK.
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