Test and Verifications Solutions Ltd
|Designation:||Manager, TVS France|
|Title:||Low Power Verification using Power State Table Coverage|
Abstract : This presentation describes low power verification principles and the use of power state table to identify invalid power states and power transitions. The presentation will show how to use the UPF power state tables to describe valid states and transitions for verification purposes. We will then explain issues related to reset states and transitional states and show how to use the power state table coverage to identify new sequences to implement.
Biography : François Cerisier has an Engineering Diploma in Digital Signal Processing from Polytech’Sophia, University of Nice-Sophia-Antipolis and over 13 years of experience in verification of IPs, CPUs and System-On-Chips and in hardware/software co-verification. François gained verification methodology expertise from industrial projects of major semiconductor companies (including Infineon, Broadcom, ST-Microelectronics, ST-Ericsson) and EDA start-ups. He is now leading Test and Verification Solutions subsidiary in France to provide verification services and consulting.
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