|Designation:||Principal Design Engineer (STMicroelectronics)|
|Title:||Real-life Low Power Verification Pitfalls and UPF 1801 for a CPF User|
Abstract : This presentation warns of some traps discovered during functional verification of real-life multi-power digital consumer SoCs. Secondly, it highlights some of the methodology changes and challenges encountered when moving from low power verification of SoCs using CPF power intent, to verification using IEEE 1801 UPF.
Biography : Paul Bailey has a science degree in Electrical and Electronic Engineering and has over 28 years of experience in designing analog and digital electronics, and software. For 16 years he has worked with RTL and digital ASIC design, implementation, and verification: from IP coding through to tapeout signoff. Paul currently works in one of the STMicroelectronics consumer product divisions in a silicon flow architecture role, leading low power SoC design and verification methodology across multiple projects.