Name:Albert Chiang
Designation:Product Marketing Manager
Title:UVM, The Next Phase

Abstract:  UVM has gained universal acceptance as the de-facto verification methodology.  One data point to support this is found in a recent unbiased study conducted by the Wilson Research Group: there was a 486% growth in UVM adoption between 2010 & 2012.  The strong growth in adoption also is reflected in industry hiring of engineers with UVM skills. In fact, UVM skills are also being sought after by non-traditional players as well.  As the design verification community starts mastering the basics of UVM, the next set of challenges awaits them. Challenges faced by advanced UVM users include reusing IP level environment for SOC verification, register testing, UVM debug, and integration with VIP.  Mentor Graphics , being one of the original and major contributors to UVM, as well as AVM and OVM, can provide solutions, products, technologies, and expertise to harness the power of UVM.   In this presentation, we will share with the audience some of the observations of UVM users around the world, their challenges, and solutions that worked.

Biography:  Albert is currently the Product Marketing Manager for the Questa Verification Platform. He has over 20 years of experience designing and verifying ASICs & ARM based SOCs.  Currently he is focused on the burgeoning field of Design Verification, where he has published and presented papers at IEEE, ARM Developer’s Conference (now ARM TechCon), DVCon and numerous public seminars worldwide.  Previously to Mentor Graphics, he was a senior design engineer at VLSI Technology, design engineer at Intel Corporation and a PMM/TMM/AE at Synopsys.  He has a BSEE from California State University and an MBA from Santa Clara University.


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