|Designation:||Staff CAE, Verification Group|
|Title:||UVM Best Practices & Debug|
Abstract: UVM (Universal Verification Methodology) tends to be a popular way to develop and reuse verification environments in IC world. It effectively guides users on how to build testbench architecture by components, sequences, TLMs, etc., and how to control the simulation flow by phasing. However, the UVM standard SystemVerilog class library with hundreds of classes provides users mass information, which is a big challenge to users. Thus this presentation demonstrates some UVM best practices to use UVM library class, and moreover, it introduces an effective way to debug UVM testbench by VCS DVE and Verdi.
Biography: Leo Fang, a Senior Verification Solutions specialist from Synopsys, has 12 years’ hands-on IC design & verification experience. He is proficient in verification methodologies like UVM/VMM/OVM, simulator tools like VCS, low power verification tools like NLP, MVTools and VSI-LP, and Verification IPs like PCIE/HDMI/Interlaken. Since He joined Synopsys in 2007, he has engaged in a lot of projects and support for Synopsys customers like Cisco, QualComm, LSI, Marvell, AMD, Atheros, Infineon, MediaTek, Realtek, Sunplus, Amlogic, HiSilicon, ZTE, Spreadtrum, etc. He received Bachelor and Master degrees in Electronic Engineering from Tsinghua University.
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