|Title:||Are you Suffering to Handle on-the-fly Events in Complex UVM Scenarios|
Abstract: UVM had experienced great adoption and growth throughout the industry for 3 years, engineers are facing a set of challenges on verification of more and more complex design. When UVM users are creating complex scenarios to verify the design features, it’s a big challenge to handle the concurrent on-the-fly events or interrupts properly and make it be vertical reused. In the presentation, we will suggest practical methodology which audience will gain solution from.
Biography: Roman Wang, a verification engineer from AMD and co-founder of DVClub Shanghai, has over 7 years’ experience in advance verification methodologies both ASIC and ARM based SOC. Prior to AMD, Roman worked in Freescale for 5 years. Roman received M.Sc. degree in Microelectronics & Solid State Electronics and 2 B.Sc. degrees(1. Measurement & Control system technology; 2. Computer Science) from Xi’an University of Technology. Roman had authored 13 technical papers in CDNLive, SNUG and Technical Journals, meanwhile contributed to Cadence Udacity Functional Hardware Verification course — Lesson 7: Reuse Methodology (UVM).
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