SystemVerilog and UVM Update
AGENDA
| 11.30 | Arrival and Networking |
| 12.00 | Introduction by Dr Michael Bartley, T&VS |
| 12.05 | Adam Sherer, Accellera UVM Working Group Secretary, |
| 12.25 | Steve Holloway, Dialog Semiconductor, Changes to the Register Abstraction Layer |
| 12.50 | Alan Fitch, Doulos, SystemVerilog Scheduling Semantics |
| 13.10 | Francois Cerisier, T&VS, Advanced scoreboarding techniques using UVM |
| 13.30 | Close and Networking |
Note : Above timings are in BST