|Designation:||Principal Verification Engineer|
|Title:||UVM Register Modelling: Advanced Topics|
Abstract : ASIC designs usually have a large number of on-chip registers which must be verified before tape-out. The UVM methodology includes a register modelling package which is designed to help simplify this task. In order to perform register modelling in UVM, several steps must be followed. These include creating a register model with an automatic generator, capturing special register behaviour, integrating the register model into a verification environment and writing register test sequences. Last year I presented my experiences with the UVM register modelling package and some recipes for creating custom behaviour. This time I will present some more advanced topics, including:
Writing register sequences.
Backdoor register access.
Multiple address maps.
Developing a coverage model.
Biography : Steve Holloway is currently Principal Verification Engineer within the IP group of Dialog Semiconductor. He has led the verification of various large-scale consumer SoC projects and has 13 years experience of Hardware Verification Methodologies including eRM, OVM and UVM. Steve has previously worked for Doulos, NXP and Trident Microsystems.