|Designation:||Principal Solutions Engineer|
|Title:||Revolutionary Debug Techniques to Improve Verification Productivity|
Debug is becoming a main bottleneck in verification. Customers are spending over 50% of their verification effort in debugging. The interactive, iterative debug methodologies of the past are losing steam. The debug paradigm must change to introduce new debug methodologies for complex SoC verification. One of such innovative methodologies is “Interactive” post process debug.
So, what’s this “interactive” post process debug stuff anyways? It can easily be defined as a combination of interactive and post process debug integrated into a single debug environment. In other words, the designer and/or the verification engineer needs to run their simulation only once after the bug has been detected. The secondary run records all needed debug data needed for the user to isolate the bug. No need to run multiple sets of simulations to find the bug… A significant savings in debug time! We will present how you can quickly step forward or backward through your source code even in a post process debug environment, or click on any line or variable directly to get to the point in time when the line executed or variable changed. And, since bugs can lurk in both the RTL as well as the testbench, we will show you how you can seamlessly navigate from HDL to HVL (e/SystemVerilog) code when exploring the root cause of issues.
Additionally, where do most designers and verification engineers spend the majority of their debug time? We have found that many people get bogged down with manually searching through their logfiles for debug. Thus, customers have requested that log file analysis capabilities must be much more interactive and connected to the debug environment with smart filtering and clickable messages that take users directly to point of interest in either the source code or the waveform database. Searching for specific values, types and verbosity levels should be quick and efficient and should be visualized easily in an effective manner.
We will explore novel debug methodologies that will allow you to:
- Step forward or backward through the simulation, or jump to a specific point in the simulation
- Investigate possible reasons why the simulation has reached a particular state through advanced go-to-cause features
- Filter all messages coming from any platform (HVL and HDL code) and explore the cause of the messages
- Explore your test environment for static and dynamic information
Liang Chen is currently working as principal solutions engineer at Cadence. He got master degree on computer science from Shanghai JiaoTong University, has been working actively in the field of digital design and verification area for 9 years, covering from communication IP to processor development. In Cadence, he is focusing on simulation performance improvement and various verification methodologies to improve verification efficiency and quality.
View the Presentation Materials: DVClub Shanghai Presentation