|Name:||Dr. Pradeep Kumar Nalla (Staff R&D Engineer – EDA formal verification tools/methodology)Dr. Srobona Mitra (Staff R&D Engineers – Formal Verification for z Processor)Sudhakar Reddy A (Engineering Manager)|
|Title:||Formal verification Applications @ IBM Enterprise Processor designs|
Abstract: Formal verification methodology adoption is growing to help logic design verification closure. This talk covers formal verification history & evolution within IBM, different formal tools/methodologies and their applications (apps) applied to internal enterprise processor design (Power, Z and System ASIC), and key results and challenges during adoption.
Pradeep Kumar Nalla, has overall ~6yrs of industry experience in VLSI field. Currently working with IBM Server Processors group since Jan 2012 as part of EDA-India Verification tools team. He is involved in development and support for Formal verification tool SixthSense. Prior to joining IBM, he was with “Atrenta India”, where he developed and supported the tool Sequential Equivalence Checking for Power optimization. He did his Ph.D. from University of Tuebingen, Germany in 2008 – on the topic – “Efficient distributed bounded property checking”
Srobona Mitra is an R&D Engineer with 2+ years experience with the India Systems and Technology Laboratory, IBM India Pvt. Ltd., Bangalore, India. She joined IBM in June 2012, and is working as part of the global formal verification team deploying the formal verification methodology on various units of System Z. She received her M.Tech. and Ph.D. degrees from the Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Kharagpur, Her PhD research was on “Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits”.
Sudhakar Reddy A, has overall ~15 yrs of industry experience in various domains – GPU/CPU/Mobile/EDA as lead/manager. Majority of his work has been in functional verification. He did his masters from IIT, Madras in Microelectronics.
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