|Name:||M V Achutha Kiran Kumar|
|Designation:||Staff Engineer, Intel|
|Title:||Embracing Formal Verification: An Intel® Graphics Experience|
Abstract: Increasing Design Complexity driven by Feature and Performance requirements and the Time to Market (TTM) constraints force a faster design and validation closure. Traditional verification processes provide a compromise between breadth of coverage and resources available. Modern formal verification techniques provide a complete coverage of the design with the available resources. Intel® Graphics Team has taken a goal to embrace formal verification in most of its verification efforts. In line with the vision, we have implemented formal techniques in various areas which include control path, data paths, RTL2RTL formal and connectivity analysis. We also have methodologies to enable formal verification at the design stage also which helped a faster churn of RTL and stabilizing it earlier. The presentation talks about the history of formal verification embrace in intel® in general and shares the experience of bringing up formal verification in graphics and the stride it to becoming the Center of expertise.
Biography: Kiran graduated from IISc, Bangalore and joined Intel through campus recruitment. He started on the famous rather infamous “Whitefield” project as RTL designer and worked on Circuit designs, Backend synthesis before exploring functional verification. He has done pre silicon verification at multiprocessor, cluster level before ramping up on Formal verification. Starting with Datapath formal verification using STE, he expanded the scope of formal verification on Graphics with Control path verification and RTL2RTL Formal equivalence verification. He was instrumental in evaluating and bringing up new tools and methodologies and his team is the “Centre of Expertise” for the formal methods in his group globally. He also runs a formal focus group for intel india which is a common platform for increasing the formal presence in different projects.
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