TVS hosted an International Design Verification Confernece in the UK in November 2011

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Mike Bartley, CEO, TVS: “Introduction”

Harry Foster, Chief Scientist for Design Verification Technology Division, Mentor Graphics: “From Volume to Velocity: The Transforming Landscape in Function Verification”

Panel Session: Our Top Verification Challenges

• Bryan Dickman, Director Design Assurance, Processor Division, ARM PDF

• Olivier Haller, Verification Methodology Manager, STMicroelectronics PDF

• Hans Lundén, Functional Verification Manager, Ericsson PPT

• Clemens Müller, Director Functional Verification, Automotive Microcontroller Business Line Infineon PDF

Mike Stellfox, SoC and System Verification Solutions Architecture Team Leader, Cadence Design Systems: “The next frontier – Addressing the Challenges of SoC Verification” PDF

Serrie Chapman, Requirements Engineering Manager, and Darren Galpin, VIP Verification Manager, Infineon Technologies: “The drive for Requirements Engineering and how it may affect verification” PDF

Mike Benjamin, Verification Consultant, TVS: “Benchmarking Functional Verification” PDF

Steve Holloway, Senior Verification Engineer, Methodologies Group, Dialog Semiconductor: “Adopting a Methodology”, How and why?” PDF

Lawrence Loh, Vice President of Worldwide Applications Engineering, Jasper Design Automation: “SOC-level Formal Verification” PDF

Nick Gatherer, Engineering Manager for Modeling, ARM: “Does ESL Have a Role in Verification?” PDF

Jean-Marc Forey, Technical Marketing Manager, SpringSoft: “Mutation-based Testing Technologies Close the “Quality Gap” in Functional Verification for Complex Chip Designs” PDF

Janick Bergeron, Synopsys Fellow, Synopsys: “Functional Verification of Today’s and Tomorrow’s SoCs” PDF