Checking that IPs and subsystems are correctly wired in the SoC is a fundamental verification tasks. Simulation and emulation tests provide some confidence that clocks and resets, bus interfaces, and other IP pins have been connected correctly. However, only static methods can deliver exhaustive verification with high efficiency. That is why formal connectivity checking has enjoyed widespread adoption. But there are still challenges. For extra-large, multi-billion gate SoCs, creating connectivity specification tables with hundreds of thousands of entries cannot be done manually. Complexity issues can lead to inconclusive results or unacceptably long runtimes. This presentation looks at how Xilinx deployed a new connectivity verification solution that addresses these challenges.
3 Key Points:
Raising the abstraction level of IP connection specifications
Automatic generation of detailed IP pin connectivity tables
Exhaustive checking of 1 Million+ connections in multi-billion gate SoCs
Sergio Marchese is technical marketing manager at OneSpin Solutions. He has 20 years of experience in electronic chip design, and deployment of advanced hardware development solutions across Europe, North America, and Asia. His expertise covers IC design, functional verification, safety standards, including ISO 26262 and DO-254, and detection of hardware Trojans and security vulnerabilities. He is passionate about enabling the next generation of high- integrity chips that underpin the Internet of Things, 5G, artificial intelligence, and autonomous vehicles.
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