Meeting tight SoC project deadlines and strict design quality requirements requires effective automation of as much verification as possible. This talk describes several proven techniques available today to help. First, design IP vendors can provide UVM testbench models and test sequences to include in a stand-alone IP testbench or a full SoC simulation. At the chip level, users can choose to control the IP blocks from C/C++ code running on embedded processors, and this can also be supplied by the IP vendor. It is also possible to automatically generate UVM or C/C++ test sequences for custom blocks, and for SoC-level structures such as registers, buses, aggregators, and bridges.
3 Key Points:
Effective and efficient SoC verification requires automation
Many aspects of IP and SoC UVM testbenches can be automated
Automation extends to system validation using embedded C/C++ code
Anupam is the founder and CEO at Agnisys. He has more than two decades of experience implementing a wide range of products and services in the high-tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel Corporation, Blackstone Consulting Group, Cadence Design Systems, and Gateway Design Automation. Anupam has earned a HighTech MBA from Northeastern University, Massachusetts, a Master’s in Computer Engineering also from Northeastern University and a Master’s in Science (Electronics) from Delhi University.
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