Cut the PS BS. Practical test synthesis for your SoC/UVM environment2018-08-16T15:33:58+00:00

DVCLUB Europe |Portable Stimulus

Cut the PS BS. Practical Test Synthesis for your SoC/UVM environment

Conference:DVCLUB Europe | Portable Stimulus | Sep 2018
Speaker:Adnan Hamid, CEO – Breker Verification Systems, Inc
Abstract:There is a lot of hype around the new Accellera Portable Stimulus Standard (PSS), which can sometimes mask its practical benefits for real environments. This presentation will demonstrate exactly how engineers can easily create and synthesize PSS graphs into SoC C-tests and transactions, as well as UVM sequences, checks and coverage models, accelerating existing verification testbenches. It will go on to discuss how coverage, profiling and debug analysis may be fed back to the specification and scenario levels, increasing effectiveness and efficiency.
Speaker Biography:Adnan is the founder CEO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor. In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors. Adnan holds twelve patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

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