|Conference:||DVClub Europe – May 2016 (click here to see full programme)|
|Presentation Title:||Improving UVM Testbench Debug Productivity and Visibility|
|Abstract:||This session will teach attendees how to debug dynamic class activity in SV/UVM, just as easily as you can with RTL signals and how to navigate complex UVM environments and quickly find your way around the code, whether your own or inherited.|
|Speaker Bio:||Alex Grove has over 20 years’ experience in the EDA industry having worked for Synopsys, ARM, Synplicity, Aldec, OneSpin Solutions, and Mentor Graphics.|
He has experience in the design and verification of ASICs and FPGAs, functional safety, and a broad knowledge of the EDA industry. After graduating from Aston University, with an honours degree in Electronic Engineering & Computer Science, Alex joined Synopsys Northern Europe to work on synthesis and test.
During his time at Mentor, Alex has worked as a product specialist for High-Level Synthesis and Virtual Prototyping and is now working as European Application Engineer for functional verification with a focus on simulation and FPGA-based prototyping.
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