Conference:DVClub Europe 2015 (click here to see full programme)
Speaker:Staffan Berg, Senior Applications Engineer
Organisation:Mentor Graphics
Presentation Title:Automating SoC-Level Tests with Portable Stimulus
Abstract:Techniques for generating verification stimulus have been around as long there have been designs to verify. As the designs being verified have become more complex, stimulus generation techniques have evolved to address the emerging requirements. From directed tests to random test generation to graph-based intelligent testbench automation, development of these stimulus generation techniques has evolved from specific verification challenges.Today, new verification challenges emerging at the SoC level. SoC-level verification is performed using simulation, emulation, and prototypes. Stimulus is often driven by the embedded processors inside the design. Existing stimulus-generation techniques, such as constrained random generation, simply don’t scale to SoC-level verification.This session will explore the emerging SoC-level verification challenges, and new portable stimulus generation techniques that raise the stimulus specification abstraction level, enable stimulus reuse across verification platforms, and bring a high degree of automation to SoC-level stimulus generation.  Topics covered will include:

  • Graph-based intelligent testbench automation
  • Portable stimulus
  • Scaling from Block to SoC verification
BiographyStaffan Berg is currently working as European Applications Engineer at Mentor Graphics in Europe, specializing in Digital Functional Verification Tools and Methodology. He has been with Mentor since 1989, working in many different fields including Real-time SW development tools, Simulation. Logic Synthesis, Formal verification and HW/SW Co-verification. Prior to joining Mentor Staffan worked as Systems Engineer at Racal-Redac, and as EDA tool developer at Ericsson Telecom. Staffan holds an M. Sc degree from the Royal Institute of Technology in Stockholm, Sweden

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