Complex designs achieve ISO26262 via the introduction of Safety Mechanisms to protect against random hardware faults that can cause a violation of a Safety Goal. The challenge is in performing a comprehensive safety analysis of the design, and proving the completeness of the analysis in an efficient manner.
This presentation will show how APIS IQ features (until now used for systematic failure mode analysis) are innovatively used to identify the potential Random Hardware Faults which can disrupt the function of a design, leading to a failure to meet a Safety Goal.
Finally, the presentation provides a suggestion on how to link this conceptual analysis to design and verification plans, thus closing the gap between architecture and verification.
Systematic collection of potential failure modes
Coverage analysis of Safety Mechanisms w.r.t failure modes
Hierarchical presentation of results to facilitate effective analysis Thereby achieving an effective (high quality) analysis in an efficient and comprehensive manner.
The speaker has extensive experience in several areas of semiconductor development, including verification, design and concept or system engineering. In her current role, she leads the activities on the architecture, specification and safety analysis of the automotive embedded flash systems, working with multiple teams spanning different countries.