Signing Off: What are your Verification Tape-Out Criteria

DVClub Europe Meeting – November 2020

Event at a Glance

  • Tuesday 24th November, 2020

  • 12:00 – 13:25 GMT

  • FREE to attend Online

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Signing Off: What are your Verification Tape-Out Criteria

IP Integration Into Complex SoCs

  • 3 verification leaders will spend 20 minutes each outlining their signoff criteria
  • In advance there will be a survey on what people use for their sign off criteria and we will present findings at the DVClub

Agenda (GMT):

TimeSession Description          Slides             Videos
12.00 GMT 17:30 ISTWelcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12.05 GMT 17:35 ISTSignoff criteria for Verification by Thinking Ahead
Nihit Chattar, Staff Verification Engineer – ARM
12.25 GMT 17:55 ISTPre-silicon Digital Verification Sign-Off for Infineon Automotive Microcontrollers
Tim Blackmore, ATV Global Verification Manager – Infineon Technologies
12.45 GMT 18:15  ISTQuis custodiet ipsos custodes? (Who watches the DV engineers? Themselves?)
Anthony Wood, Formal Team Lead – Graphcore
13.05 GMT 18:35 ISTWilson Research Survey of ASIC/FPGA signoff criteria, Findings from Harry Foster – Mentor Graphics
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
Download Slides Download Research DataView
13.25 GMT 18:55 ISTClose

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.


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