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DVClub Europe – September 2020: IP Integration Into Complex SoCs

IP Integration Into Complex SoCs

DVClub Europe Meeting – September 2020

Event at a Glance

  • Tuesday 08th September, 2020

  • 12:00 – 13:20 BST

  • FREE to attend Online

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IP Integration Into Complex SoCs

IP Integration Into Complex SoCs

SoC designs typically incorporate a range of (in-house and external) IP, all connected via different bus structures. In this DVClub we consider the effectiveness and efficiency of different verification techniques to ensure the IP has been correctly integrated.

Agenda (BST):

TimeSession Description          Slides             Videos
12.00 PM BST (04:30 PM IST)Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, T&VS
12.05 PM BST (04:35 PM IST)IP Integration Verification in Extra-large (XL) SoCs 
Sergio Marchese, Technical Marketing Manager, OneSpin Solutions
12.25 PM BST (04:55 PM IST)Solving system-level challenges of integrating PCIe gen 4 RC IP
Nick Heaton, Distinguished Engineer, Cadence
12.45 PM BST (05:15 PM IST)Yet to be confirmed
13.05 PM BST (05:35 PM IST)Close

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

Sponsors

DVCLUB Europe is made possible through the generosity of our sponsors.