IP Integration Into Complex SoCs

DVClub Europe Meeting – September 2020

Event at a Glance

  • Tuesday 08th September, 2020

  • 12:00 – 13:25 BST

  • FREE to attend Online

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IP Integration Into Complex SoCs

IP Integration Into Complex SoCs

SoC designs typically incorporate a range of (in-house and external) IP, all connected via different bus structures. In this DVClub we consider the effectiveness and efficiency of different verification techniques to ensure the IP has been correctly integrated.

Agenda (BST):

TimeSession Description          Slides             Videos
12.00 BST 16:30 ISTWelcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, T&VS
12.05 BST 16:35 ISTIP Integration Verification in Extra-large (XL) SoCs 
Sergio Marchese, Technical Marketing Manager, OneSpin Solutions
12.25 BST 16:55 ISTSolving system-level challenges of integrating PCIe gen 4 RC IP
Nick Heaton, Distinguished Engineer, Cadence
12.45 BST 17:15  ISTPower Control Verification Challenges In Arm-based SoCs
Deepak Joshi, Staff Verification Engineer, ARM
13.05 BST 17:35 ISTVerification and Integration challenges in RISC-V SOC
Suresh Babu Pushparajan, Tessolve
Lavanya J, Incore Semiconductors Pvt Ltd
13.25 BST 17:55 ISTClose

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.


DVCLUB Europe is made possible through the generosity of our sponsors.