The Universal Verification Methodology (UVM)
In this DVClub meeting our speakers will share their experiences of using UVM (the Universal Verification Methodology) and then open the floor for discussion followed by the usual networking opportunities
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The Universal Verification Methodology (UVM) is an Accellera standard to enable both the development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. The Accellera industry body provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).