The cost of detecting and fixing bugs increases exponentially as a design moves through development. IP and SoC designers use commercial, in-house, and sometimes self-made tools and test benches to explore and check their code prior to commit. Formal-powered applications have enjoyed widespread adoption over the last decade for their ease-of-use and capabilities to uncover interesting scenarios automatically. This presentation gives an overview of how designers use formal verification, and delves into powerful approaches such as agile RTL development, automated design exploration, and exhaustive verification of optimizations with sequential EC.
3 Key Points:
Agile RTL development
RTL-2-RTL EC to check design optimizations
Sergio Marchese is technical marketing manager at OneSpin Solutions. He has 20 years of experience in electronic chip design, and deployment of advanced hardware development solutions across Europe, North America, and Asia. His expertise covers IC design, functional verification, safety standards, including ISO 26262 and DO-254, and detection of hardware Trojans and security vulnerabilities. He is passionate about enabling the next generation of high-integrity chips that underpin the Internet of Things, 5G, artificial intelligence, and autonomous vehicles.
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