ISO 26262-5 requires the determination of hardware safety metrics, including SPFM and LFM. Latent and residual diagnostic coverage are also important metrics to assess the effectiveness of safety mechanisms. This presentation introduces a systematic, largely automated process to compute safety metrics. It covers accurate fault analysis in safety mechanisms with and without error-correcting capabilities. The approach scales to large SoCs and significantly reduces the need for manual analysis and fault simulation. Experiences and results of its application to a number of ASIC and FPGA gate-level netlist designs are reported.
3 Key Points:
Impact of faults in safety mechanisms on the hardware safety metrics
Results on ASIC/FPGA gate level netlists
Sergio Marchese is technical marketing manager at OneSpin Solutions. He has 20 years of experience in electronic chip design, and deployment of advanced hardware development solutions across Europe, North America, and Asia. His expertise covers IC design, functional verification, safety standards, including ISO 26262 and DO-254, and detection of hardware Trojans and security vulnerabilities. He is passionate about enabling the next generation of high-integrity chips that underpin the Internet of Things, 5G, artificial intelligence, and autonomous vehicles.
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